The present invention relates to electronic memory devices, and, more particularly, to synchronous output buffers, especially for non-volatile memories.
It is known in the art that the buffers of a non-volatile memory generally display the data stored in the memory. The buffers also provide a high-impedance (tristate) condition of the memory when it is necessary to transfer to other memory units the control of an external buffer which interfaces with the memory. The networks that are generally used provide the buffer function by logic chains on multiple levels. The length of the implemented chains include transit times which, despite being modest in standard power supply conditions (e.g., 5 V), become significant at lower voltages (e.g., 3 V).
Moreover, conventional buffers immediately display the data after it is received. This causes difficulties in deferring switching of the output stages to provide appropriate protocol synchronizations (burst-type reading). The need for high speeds (even at low power supply voltages) and for easy adaptation (even to synchronous protocols) may render conventional output buffer structures inefficient.
An object of the present invention is to provide an output buffer which has a minimal data transit time.
Another object of the present invention is to provide an output buffer in which data item updating is performed by an appropriate pulse that can be synchronized with external controls.
A further object of the present invention is to provide an output buffer in which it is possible to defer updating an external display of a new data item in the buffer.
Yet another object of the present invention is to provide an output buffer that allows a last read data item to be kept in the memory.
Still another object of the present invention is to provide an output buffer that allows limiting the switching noise of the output stage.
An additional object of the present invention is to provide an output buffer that is highly reliable and relatively easy to manufacture at competitive costs.
These and other objects which will become more apparent hereinafter are provided by an output buffer, particularly for non-volatile memories, including a push-pull output stage, a first data latch circuit receiving as an input data from an external data bus which connects at least one memory to the first data latch circuit, first and second activation paths for the activation of the push-pull stage, first and second circuits for enabling the push-pull stage, first and second circuits for disabling the push-pull stage, and second and third data latch circuits connected to the push-pull stage.
More specifically, the first and second activation paths may be connected to the first data latch circuit. Furthermore, the first and second circuits for enabling the push-pull stage may be connected between the first data latch circuit and the push-pull stage. The first and second circuits for disabling the push-pull stage may be respectively connected between the first and second activation paths and the first data latch circuit and may receive as inputs an output enable signal and a data updating signal. Additionally, the second and third data latch circuits may be connected between the push-pull stage and, respectively, the first and second activation paths for the activation of the push-pull stage.